Hardware Acceleration of Adaptive Neural Algorithms

Laboratory Directed Research and Development Grand Challenge

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The Hardware Acceleration of Adaptive Neural Algorithms (HAANA) Project is focused on developing neural-inspired algorithms to challenging pattern recognition problems in the imaging and cybersecurity domains. We have developed a non-spiking algorithm termed “neurogenesis deep learning” that incorporates the functionality of neurogenesis into the network structure to improve the robustness of deep learning (DL) for pattern recognition applications (Draelos et al., IJCNN 2017). This approach enables autoencoder network structures to reconstruct newly-learned data classes (e.g., handwritten digits) while maintaining the representations of previously learned data classes. We have also developed spiking algorithms that compute mathematical functions exactly, at times translating data from one domain into the time domain to improve algorithm performance. Severa et al. (ICRC 2016, doi: 10.1109/ICRC.2016.7738681) recently demonstrated a spiking neural network algorithm for computing cross-correlations of functions in constant time.

     In addition, the team is leveraging advances in memory storage devices to reduce the power consumption and areal footprint of hardware implementations of neural algorithms.  Mickel et al. (Adv. Mater. 2014; doi: 10.1002/adma.201306182) detailed a model of resistive switching in a filamentary TaOx-based microdevice. Our thermoelectric model matched the resistance vs. current curves for a number of filament-switching material systems including HfOx and TiOx. We have also developed novel resistive switching device architectures with analog characteristics for neuromorphic computing applications (Fuller et al., Adv. Mater. 2016; doi: 10.1002/adma.201604310). This Li-ion synaptic transistor for analog computation (LISTA) device has a three-terminal architecture that enables multiple stable resistance states for storing neural network algorithm weight values.

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