Sandia Neuroscience

Neuromorphic Hardware in Practice and Use

2018 WCCI Workshop

Submission Information

Submit papers here

Deadline: April 30, 2018


Craig M. Vineyard, PhD
Sandia National Laboratories*

William M. Severa, PhD
Sandia National Laboratories*

Kristofor D. Carlson, PhD
BrainChip Inc.


List of committed program committee members

James B. Aimone, PhD – Sandia National Laboratories

Conrad D. James, PhD – Sandia National Laboratories

Garrett Kenyon, PhD – Los Alamos National Laboratory

Dhireesha Kudithipudi, PhD - Rochester Institute of Technology

Catherine Schuman, PhD – Oak Ridge National Laboratory 

Description of the workshop


This workshop is designed to explore the current advances, challenges and best practices for working with and implementing algorithms on neuromorphic hardware. Despite growing availability of prominent biologically inspired architectures and corresponding interest, practical guidelines and results are scattered and disparate.  This leads to wasted repeated effort and poor exposure of state-of-the-art results.  We collect cutting edge results from a variety of application spaces providing both an up-to-date, in-depth discussion for domain experts as well as an accessible starting point for newcomers. 

Goals & Objectives

This workshop strives to bring together algorithm and architecture researchers and help facilitate how challenges each face can be overcome for mutual benefit. In particular, by focusing on neuromorphic hardware practice and use, an emphasis on understanding the strengths and weaknesses of these emerging approaches can help to identify and convey the significance of research developments. This overarching goal is intended to be addressed by the following workshop objectives: 

1) Explore implemented or otherwise real-world usage of neuromorphic hardware platforms

2) Help develop 'best practices' for developing neuromorphic-ready algorithms and software

3) Bridge the gap between hardware design and theoretical algorithms

4) Begin to establish formal benchmarks to understand the significance and impact of neuromorphic architectures

Relevance to IEEE WCCI

IJCNN covers a wide range of topics in the field of neural networks and neural computation. In recent years, these topics have expanded to include biologically inspired hardware implementation research as well. The rapidly evolving need for hardware accelerators to enable the algorithmic and theoretical advances being made by WCCI attendees and participants also necessitates an understanding of how the interplay of algorithms and architectures in the form of neuromorphic computation is advantageous. A better understanding of the algorithm and architecture interplay also allows for the development of meaningful benchmarking which can further highlight the significance of research advances. 

We expect three primary groups to comprise the audience.

  • Neuromorphic Hardware Experts: Recently a new field of neuromorphic platforms has become available, either at prototype or release stages. These platforms originate from a variety of groups within industry, academia and government.  Hardware designers and platform stakeholders have  a keen interest in early adoption, algorithms and applications as well as comparative and case studies.
  • Spiking Neural Network Algorithm Designers: As is evidenced by the growing presence of spiking neural networks at conferences such as IJCNN, biologically inspired spiking neural networks offer new and expanding capabilities. However, these algorithms are rarely designed following particular hardware constraints, and this creates a challenge when implementing the algorithms in practice.  By expounding on neuromorphic implementations of spiking networks, algorithm designers stand to expand both utility and practicality.
  • Low-Power and Embedded Application Spaces: Neuromorphic platforms offer compelling improvements in performance-per-Watt. However, these numbers are often vendor-supplied and rarely include difficulties involved with algorithm porting.  This workshop will offer a true-to-life story of the process, benefits and pitfalls of using neural networks on these up-and-coming platforms.

Scope and Topics:

Neuromorphic hardware; benchmarks and comparisons; applications, software, and toolkits; algorithms; workflows and integration 

Workshop duration, format, activities, and schedule

This half day workshop will consist of a brief overview of the various approaches to neuromorphic computation and motivate the need for applied results and benchmarks to properly characterize the significance of such approaches. Following the introduction will be a series of talks interleaving invited keynote speakers and contributed talks. A poster and demonstration session will conclude the session while encouraging discussion amongst the participants.                                  

13:00 - 13:20

Welcome and Opening Overview Talk

13:20 – 13:50       

Invited Talk

14:00 – 14:20

Contributed talk

14:20 – 14:40

Contributed talk

14:40 – 15:00

Contributed talk

15:00 - 15:15


15:15 – 15:45                                        

Invited Talk

15:45 – 16:00   

Contributed talk

16:00 – 16:15

Contributed talk

16:15 – 16:30

Contributed talk

16:30 – 17:00

Invited Talk

17:00 – 17:30

Posters & Demonstrations 


Submission Guidelines and Timeline

The workshop requests submissions to follow IEEE conference style similar to the main conference.  Papers should be submitted in pdf format with a maximum length of 2 pages (excluding references and acknowledgements).  Appendices are not permitted beyond the 2 page limit.  Submissions will be selected according to reviewer's comments and scoring with emphasis on quality, novelty, appropriateness for the workshop and potential impact on the field.  

30 April 2018

Workshop submission deadline

1 May 2018

Submissions sent to reviewers

10 May 2018

Decisions sent to submission authors

Preliminary list of invited speakers

Jeff Krichmar, PhD (UC Irvine) – Jeff’s research focuses upon neurorobotics, embodied cognition, biologically plausible models and learning and memory, and the effect of neural architecture on neural function.

Dhireesha Kudithipudi, PhD (Rochester Institute of Technology) – Dhireesha’s research focuses on ultra-low power circuits and microarchitures and 3D-ICs, emerging memory technologies, and design of biologically inspired architectures. 

Short biographical sketch for each organizer

Craig M. Vineyard, PhD. received the B.S., M.S., and PhD. degrees in computer engineering from the University of New Mexico with a concentration in Computational Intelligence. As a research scientist at Sandia National Laboratories in the Data-driven & Neural Computing department he has worked on neural network modeling and simulation, the development of information theoretic analysis techniques, complex systems modeling, neuromorphic computing architecture development, machine learning algorithms, and game theory research. He has authored over a dozen papers in those respective fields.

William M. Severa, PhD. received his PhD in mathematics from the University of Florida where he studied s-adic infimax systems. He has a background in topological dynamical systems and symbolic dynamics and is particularly interested in mathematically-rigorous neural coding frameworks and accelerating scientific computing on neuromorphic hardware.  Recently, William has been exploring expanding the utility of neural computing platforms via accessible software frameworks.

Kristofor D. Carlson, PhD. is a Senior Research Scientist at BrainChip, a neuromorphic computing company focused on software and hardware solutions in Aliso Viejo, California. Dr. Carlson received both his BS (in 2003) and PhD (in 2011) in Physics from Purdue University. Before joining BrainChip, he held postdoctoral positions at the University of California, Irvine and Sandia National Laboratories where he participated in several research projects in the fields of computational neuroscience and neuromorphic engineering. His past research topics include synaptic plasticity and homeostasis, the parallelization and optimization of large-scale neural network models, algorithm design for neuromorphic hardware, and the application of uncertainty quantification and sensitivity analysis methodologies to neural models.